The subject system and method are generally directed to an efficient timing analysis of a multiple-voltage circuit design.
Signals do not move instantly through a circuit, but experience delay as they travel through the components and interconnections. If two signals, such as a data signal and a corresponding clock signal, arrive at the same circuit component too far out of sync with each other, they will interact in unexpected ways and the component will not operate as intended, causing a timing violation. Timing analysis is therefore commonly employed during a design phase of the circuit, as part of a sign-off process, to confirm that the signals will be properly synchronized under the various conditions that the circuit can be expected to experience.
One of the conditions that can affect the speed of a signal is the supply voltage for the components. If a range of supply voltages are applicable to certain components, these components should be tested to determine the timing under at least both the maximum and minimum of this range.
These tests are complicated by multiple-voltage circuit designs. When different components in the circuit require different voltage sources and/or supply voltage ranges, differing voltage domains, or power domains, are created, and it will be necessary to re-analyze the circuit for each combination of voltages. These combinations grow exponentially in number in relation to the number of domains, such that even a small number of voltage domains can dramatically increase the duration of the required testing.
One existing response to this issue involves reducing the number of combinations tested, based on likelihood that a timing violation will be detected in each. However, a likelihood is not a guarantee, and timing violations may remain undetected under this approach. There is therefore a need to efficiently reduce voltage-based testing required for timing analysis of a multiple-voltage design, while still testing all supply voltage combinations which could create a timing violation.
Another existing response involves testing under the maximum and minimum of a single broader range encompassing all ranges in the design. This approach frequently results in detection of “false positive” violations, as individual components are tested under supply voltages they will not experience in reality, and under timing constraints and other requirements that are likewise inapplicable. There is therefore a need to efficiently reduce voltage-based testing required for timing analysis of a multiple-voltage design, without testing under inapplicable conditions.